1. Field of the Invention
This invention relates to flash memory arrays in general, and more particularly to the design and fabrication of flash EPROM arrays having a well contact structure to collect substrate current and provide a uniform well voltage during programming and erase operations.
2. Description of the Prior Art
Semiconductor memories are considered one of the crucial microelectronics components for mainframe computers, PCs, telecommunications, automotive and consumer electronics, and commercial and military avionics systems. Semiconductor memory devices can be characterized as either volatile random access memories (RAMs) or nonvolatile memory devices (NVMs). Nonvolatile memory data storage may be permanent or reprogrammable, depending on the device design.
The first category of NVMs consists of read-only memory (ROM), a memory device containing fixed data patterns determined at fabrication. Typically, ROMs are made using a process called mask programming, by which data is typically stored in the ROM at one of the final process steps. Thus, conventional ROMs are also known as mask ROMs.
In contrast to mask ROMs in which the data must be stored in the device during fabrication, a programmable read-only memory (PROM) allows the user to electrically program the data into the memory. A typical PROM cell can be programmed only once. For example, a typical bipolar-junction transistor (BJT) PROM involves the use of polysilicon fuses to connect the emitter to the corresponding digit line. Depending on the desired content of the memory cell, these fuses are either left intact or blown by a large current during programming. Obviously, such a programming step is irreversible.
To improve the conventional non-erasable PROM, several erasable NVMs have been developed, including the erasable programmable read-only memory (EPROM), the electrically alterable read-only memory (EAROM), the electrically erasable programmable read-only memory (EEPROM or E.sup.2 PROM), the nonvolatile static random access memory (NVRAM), and the flash memory. Each of these erasable-programmable semiconductor memory devices may be used in a variety of applications. For example, low-density EAROMs (less than 8 k) are used in consumer radio tuners and automotive engine controllers, while mid-density EEPROMs are used in changeable "softable" storage systems.
One of the most important erasable-programmable NVMs is the flash memory device, in which the contents of all memory array cells can be erased simultaneously through the use of an electrical erase signal. A flash memory can be based on either the EPROM or E.sup.2 PROM technology; the selection between the two requires tradeoffs between the higher density of the EPROM technology and the in-circuit programming flexibility of the E.sup.2 PROM technology.
The structure of a flash memory cell is essentially the same as that of an EPROM or E.sup.2 PROM cell. Thus, a floating gate, typically located between a control gate and a substrate, is used to store electrical charges that represent a data bit. In addition, the oxide between the control gate and the substrate in a flash memory cell is generally thinner than that of an EPROM memory cell and comparable to the tunnel oxide in some E.sup.2 PROM memory cells, to make electrical erase practical.
FIG. 1 is a cross-sectional view of a conventional stacked-gate flash EPROM memory cell transistor 10 as fabricated in a flash EPROM array. Typically, the substrate 12 is a single-crystal silicon wafer having a first conductivity type dopant, e.g., the p-type. The substrate 12 has a source region 14 and a drain region 16, both doped with a second conductivity type dopant, e.g., the n-type. A channel region 18 is defined by the near-surface area of the substrate 12 between the source 14 and the drain 16.
The flash EPROM cell shown in FIG. 1 has two gates: the floating gate 20 and the control gate 22. Both the floating gate 20 and the control gate 22 are typically made of the same material, e.g., polysilicon. Regions of dielectric material (e.g., silicon dioxide) 24 are deposited above the substrate 12 and between the floating gate 20 and the control gate 22. The dielectric (oxide) layer between the substrate 12 and the floating gate 20 is the tunnel oxide layer 26. When carrying no charges, the floating gate 20 has no influence on the electrical field generated by the control gate 22 in the channel region 18. However, if the floating gate 20 is charged with electrons, these electrical charges in the floating gate 20 will generate in the channel region 18 an electrical field opposite to the field generated by an active control gate 22, thus raising the threshold voltage of the flash memory cell, i.e., the gate-to-source potential difference required to turn on the cell. Following the convention used in EPROM technology, the device charging operation is typically referred to as the "programming" operation while the discharging operation is typically referred to as the "erase" operation.
To program the above flash EPROM cell transistor 10, a typical control gate voltage of 9-12 V is applied to the control gate 22, a typical drain voltage of 5-6 V is applied to the drain 16, and the source 14 is grounded. These programming voltages enable hot electrons in the channel region 18 to overcome the energy barrier between the substrate 12 and the tunneling oxide layer 26, and cause these electrons to be injected onto the floating gate 20 to represent a data bit. This process is the so-called channel hot electron injection programming.
A typical way to erase the above flash EPROM cell transistor 10 is source erase, by which a control gate voltage of approximately -10 V and a source voltage of approximately 5 V are respectively applied while the drain 16 is allowed to float. These erase voltages enable electrons to be driven from the floating gate 20 to the source 14, typically via the Fowler-Nordheim tunneling mechanism.
As microelectronics components including semiconductor memories are constantly shrinking in size, it is desirable to reduce the size of the channel region 18. However, the above erase operation of the conventional flash memory cell 10 imposes a significant restraint on the ability to reduce the scale of the flash memory device. This is because during source erase a conventional flash memory cell 10 creates a band-to-band tunneling leakage current at the source 14, making it difficult for the power supplies to provide sufficient current for cell erasure.
To overcome the aforesaid restraint imposed by the leakage current, a double-diffused implant (DDI) has been introduced at the source region, i.e., a "graded n+/n source region, such that band-to-band tunneling and the associated source leakage current can be reduced. Thus, as shown in FIG. 2, a lightly doped n-type implanted region 29 is formed along the outer periphery of a heavily doped n+-type implanted region 28; the two implanted regions 29 and 28 collectively constitute a DDI to serve as the source 30 of the flash memory cell 10. The channel region 18 in FIG. 2 is somewhat reduced in comparison to that shown in FIG. 1.
Although the use of a DDI source region allows shrinkage of memory cells to a certain extent, it is also apparent from FIG. 2 that the presence of the outer implanted region 29 ultimately imposes a limit on how far the reduction of the channel can go. It is, therefore, desirable to find some other ways to reduce the channel size. In this regard, channel erase has been proposed as an alternative to the conventional source erase process. Channel erase is accomplished by creating Fowler-Nordheim tunneling from the floating gate of a memory cell to its substrate rather than its source (as in source erase). An advantage of channel erase is the absence of the band-to-band tunneling leakage current during erase operations.
To implement effective channel erase, implanted wells are typically used to provide isolated regions in the substrate. As shown in FIG. 3, a p-type well 42 provides a region under an array of flash EPROM memory cells 40. This p-well 42 is encompassed by an n-type well 44 and isolated from the remainder of the substrate 12 (i.e., a double-well structure). A p+-type tap region 46 is located within the p-well 42 to provide connection between an external power supply (not shown) and the substrate 12 through a channel line 48.
During a channel erase operation, a potential difference is created by applying a control gate voltage of approximately -8 V to a given memory cell 10a while providing a channel voltage of approximately 8 V to the channel line 48 of the array 40. This potential difference causes electrons to be driven from the floating gate 20a of the given memory cell 10a through its channel 18a, the p-well 42 and the tap 46 into the channel line 48, thus completing the erasure of the charges on the floating gate 20a.
Typically, the p-well 42 is lightly doped with a p-type conductivity dopant and as a result has a relative high electrical resistance. Thus, depending on the distance from the channel of each memory cell 10 of the array 40 to the tap 46, electrical resistance differs from cell to cell in the array 40, signifying an IR drop from one cell to the next and an overall voltage variation across the p-well 42 and the array 40. This local variation of well voltage or potential has several adverse consequences. First, it causes reductions in the speeds of programming and erase. Second, it may trigger several unintended bipolar effects, e.g., snap back due to turn-on of parasitic bipolar transistors and latchup of parasitic silicon-controlled rectifier (SCR) structures. Third, RC delay along high-resistance conductive paths, particularly for those cells distant from the tap region 46, prevents fast changes in the well potential when switching from one operation mode to the other.
An additional characteristic of the aforesaid flash memory array 40 is that a large amount of substrate current is typically generated during either the channel electron programming or the channel tunneling erase. This large substrate current can de-bias the p-well 42, further increasing the sheet resistance (and the associated IR drop) along the conductive paths and aggravating the programming or erase process.
Although multiple tap regions spaced periodically along the memory array have been utilized to reduce electrical resistance along the conductive paths and well voltage variations, such multiple tap regions diminish the overall area for cell layout, thus substantially nullifying the underlying reason for choosing channel over source erase.
In another attempt to counter the aforementioned problems in connection with channel erase of a flash EPROM device, U.S. Pat. No. 5,541,875 issued to Liu et al. and entitled "High Energy Buried Layer Implant to Provide a Low Resistance p-Well in a Flash EPROM Array," discloses the use of a p+ buried layer implant inside a p-well of a flash EPROM array to provide a low resistance path between channels of the memory cells, thus enabling erase to be performed by supplying a voltage potential difference between the gate and the substrate. U.S. Pat. No. 5,541,875 is incorporated herein by reference. Although the use of a high-energy buried layer reduces the large sheet resistance typically occurring within an isolated well of a substrate in which flash EPROM memory cells are formed, the remaining sheet resistance is still relatively large compared to doped source/drain regions or metal lines, nor does it eliminate the need for well taps inside the array. Furthermore, the formation of the buried high-energy layer requires not only extra processing steps but also costly high energy (MeV level) implant equipment; both these requirements increase the manufacturing cost of such flash memory cell arrays.
Another method of erasing a flash EPROM array is disclosed in U.S. Pat. No. 5,615,152, issued to Bergemont and entitled "Method of Erasing a High Density Contactless Flash EPROM Array." In this patent, the channel erase operation is facilitated by a thin tunnel oxide formed between a p-well located in a substrate and the overlying polysilicon gate EPROM cells. The channel erase of a selected row of EPROM cells is accomplished by allowing all bit lines to float, applying a negative erase voltage to the word line of the selected row, and holding the substrate at the supply voltage. U.S. Pat. No. 5,615,152 is also incorporated herein by reference.
Another nonvolatile memory array configuration that includes double implanted wells is the so-called common source NOR NVM array. FIG. 4A is a layout representation of a typical common source double-well array 50, in which n+ diffused Vss metal common source lines 52 are placed every 16 to 64 columns (i.e., metal bit lines 54) in the array 50 to provide connections 56 to n+ source buses 58. All the Vss common source lines 52 and the bit lines 54 are parallel to each other. The source buses 58, also essentially parallel to each other, are in addition essentially parallel to the polysilicon word lines 60. The bit lines 54 are essentially orthogonally superposed above the word lines 60. Each of the metal bit lines 54 provides connections 62 to the individual n+ drain areas 64. FIG. 4B is a cross-sectional representation of the NVM array 50 along line A--A in FIG. 4A. Thus, the array 50 comprises a double-well configuration (i.e., a p-well 42 inside a deep n-well 44) formed within the near-surface region of a p substrate 12. The n+ diffused source bus 58 is encompassed by the p-well 42 and is connected to the metal source line 52 through a contact structure 56, typically a tungsten bus-to-line contact plug, located essentially within the dielectric region 24. A conventional common-source NVM array is typically programmed through the channel hot electron injection mechanism and erased through the source erase mechanism.
In sum, even though the above prior-art flash memory technologies have solved a number of problems associated with conventional flash memory arrays, several problems still exist during the erasure of stored information in such flash memory array cells. First, the aforesaid local well potential variation generally causes reductions in the speeds of programming and erase. Second, the variation of well potential often triggers undesirable bipolar effects, e.g., snap-back and latchup. Third, high-resistance conductive paths, particularly for those cells distant from the tap regions, prevent fast switching of operation modes due to RC delays along such paths.